Commit 79a75014 authored by Marek Behun's avatar Marek Behun

spi: mvebu_a3700_spi: Fix clock prescale computation

The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong. The first condition should also take care
of the 0x1f value.
Signed-off-by: Marek Behun's avatarMarek Behún <marek.behun@nic.cz>
parent 9b886386
......@@ -181,7 +181,7 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
data = readl(&reg->cfg);
prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
if (prescale > 0x1f)
if (prescale >= 0x1f)
prescale = 0x1f;
else if (prescale > 0xf)
prescale = 0x10 + (prescale + 1) / 2;
......
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